A CPU made from read only memory (ROM)

How?

Read this article ROM + ROM + … + ROM = CPU

A LUT anatomy

Borrowed from The MCU guy's introduction to FPGAs: The Hardware

Time-borrowing a clock cycle

A picture from Xcell Daily Blog

D flip-flop anatomy

DRAM Controllers for System Designers

A worth reading article outlining basic blocks of a DRAM controller.

https://www.altera.com/solutions/technology/system-design/articles/_2012/dram-controller-system-designer.html

The following two figures were borrowed from 

https://www.synopsys.com/cgi-bin/proto/pdfdla/pdfr1.cgi?file=optimizing-ddr-efficiency-p1-wp.pdf

CS150 Components and Design Techniques for Digital Systems

http://www-inst.eecs.berkeley.edu/~cs150

Blocking vs Non-Blocking assignment

Just for the record. Borrowed from MIT's Complex Digital Systems course.

Setup and hold time for D flip-flop

For those interested in nature of setup and hold time for D flip-flop there is a good explanation at www.edn.com,  just follow the link Understanding the basics of setup and hold time

I borrowed two illustrations that show the reason for setup and hold time

Reason for SETUP Time:

The time it takes data D to reach node Z is called the setup time.

Reason for HOLD Time:

The darkened line shows the conducting path for hold time.

For the reference the definition for propagation and contamination delays borrowed from here ( (c) 6004 MIT )

  Altogether,  the illustrations from here ( (c) Nilesh Goel )

Setup and Hold Time for D flip-flop

Combinational Propagation and Contamination Delay